The present invention relates to a method and a device having a processor module for controlling operating sequences, in particular in an engine control unit in a motor vehicle, peripheral elements being selected or driven to control the operating sequences.
To select or address peripheral elements, in particular bus devices in a bus system, processor modules, controllers in particular, make a plurality of selection interfaces or select lines available so that one peripheral element or bus device can be addressed with each select line. A bus device is thus selected or addressed by activation of its respective select line. The number of possible bus devices or peripheral elements that can be addressed by the processor module is thus limited, the limit being determined by the number of select lines or select signals made available by the processor module.
To expand the number of bus devices, a code is generated from a number of select signals. This code must then be decoded again by additional hardware, usually a decoder module. The required decoder logic unit entails an increased complexity in terms of circuitry, leading to higher costs and greater space requirements for the circuitboard.
Use of such a decoder logic unit is described in the article xe2x80x9cEPROM decoder for device selectionxe2x80x9d by K. J. Whiteley in the technical journal Electronic Engineering, volume 58, number 714, page 36, of June 1986. Usually a number of TTL modules will be hardwired as the decoder logic to represent the select function. This article describes selection or control of individual peripheral modules by an EPROM. If the number of select outputs or select interfaces of the EPROM is too low in comparison with the number of peripheral modules to be controlled, the selection options are expanded with the help of a decoder module, namely a 4:16 decoder here, which is connected in between. Thus, by using the decoder module, more than the maximum possible number of peripheral modules can be selected or driven via the EPROM.
The design of such address decoding using TTL modules is also described in the technical book PC-gesteuerte Messtechnik [PC-controlled measurement technology] by Klaus Dembowsky of 1993, published by MarktandTechnik Buch- und Softwareverlag GmbH and Co. under ISBN No. 3-87791-516-7. The design of decoder circuits using logic modules, TTL modules, comparator modules or PAL (programmable array logic) modules is described on pages 58 through 65.
Here again, the required decoder logic means more complex circuitry, leading to higher costs and more space required for the circuitboard.
This complex circuitry is to be avoided according to the present invention.
The present invention is based on a method and a device having a processor module for controlling operating sequences, in particular in an engine control unit in a motor vehicle. Peripheral elements here are selected by a processor module having a predetermined number of select interfaces by select signals output over these select interfaces, the peripheral elements also transmitting instructions or commands and/or data over at least one information interface of the processor module.
Advantageously, selection identifiers are assigned to the instructions and transmitted together with them. The peripheral element or elements are thus selected by a select signal and the selection identifier. It is advantageous that this makes it possible to expand the number of peripheral elements that can be controlled or addressed, in particular bus devices, without requiring any additional hardware. Thus, for example, an SPI (serial peripheral interface) bus as well as other comparable bus systems can be expediently expanded without any increased cost or increased circuit complexity.
Thus, a plurality of peripheral elements can preferably be connected to one select interface of the processor module and nevertheless be selected or addressed individually, the peripheral elements connected to the same select interface preferably being different from one another.
The selection identifier and the instruction can be transmitted to advantage in digital form as an entity composed of individual binary signals (bits), the selection identifier replacing a portion of the bits of the instruction having a predetermined bit length so that the transmitted selection identifier and instruction as an entity have the same number of bits as the instruction alone previously.
As an advantageous refinement, if the same number of instructions or commands should also be available after allocation of the selection identifier, the number of bits in the entity of the selection identifier and instruction is increased by the number of bits in the selection identifier. For example, if the command or instruction is transmitted in a data frame, the data frame is thus enlarged or the bit content of the frame is increased.
It is thus possible in an advantageous manner to select or address a greater number of peripheral elements or bus devices than would correspond to the number of select interfaces of the processor module by expanding the bus instruction words or bus command words by one or more select bits, so the number of possible bus devices, i.e., peripheral elements, is increased without any additional hardware.